The electronics industry continues to rely upon advances in semiconductor technology to realize higher-function devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices has been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS, n-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions.
One important step in the manufacture of such devices is the formation of isolation areas to electrically separate the electrical devices or portions thereof, that are closely integrated in the silicon wafer. While the particular structure of a given active device can vary between device types, a MOS-type transistor generally includes source and drain regions and a gate electrode that modulates current flowing in a channel between the source and drain regions. Unintended current should not flow between the source and drain regions of adjacent MOS-type transistors. However, during the manufacturing process, movement of dopant atoms, for example, of boron, phosphorus, arsenic, or antimony, can occur within the solid silicon of the wafer. This movement is referred to as diffusion. The diffusion process occurs at elevated temperatures where there is a concentration gradient between dopant atoms external to the silicon wafer and those dopant atoms within the silicon wafer. Diffusion processes at elevated temperatures are typically utilized when forming p-type and n-type regions of a silicon integrated circuit device.
A technique referred to as "trench isolation" has been used to limit such flow. A particular type of trench isolation is referred to as shallow trench isolation (STI). STI is often used to separate the respective diffusion regions of devices of the same or opposite polarity type (i.e., p-type versus n-type).
In forming the STI regions, one technique involves the layering of dielectric films on a silicon substrate. A prior art process begins with a silicon substrate, upon which a thin layer of silicon dioxide is formed. In an example process, about 100 .ANG. of SiO.sub.2 is deposited on the silicon substrate. Following the oxide deposition, a substantially thicker layer of silicon nitride is deposited upon the thin oxide layer. In the example process, the process deposits about 1800 .ANG. silicon nitride. Through photolithography, the STI regions are masked with a photoresist. An etch selective to the SiN/SiO.sub.2 stack is performed until the silicon substrate is exposed. The photoresist mask is then stripped off. Using the SiN as a mask, the process etches shallow silicon trenches into the substrate. The opened trenches typically receive a fill deposition of high-density plasma (HDP) oxide. In an example process, oxide is deposited at a thickness of between about 6000 .ANG. to 9000 .ANG. to fill trenches whose depths range from about 2500 .ANG. to 3500 .ANG.. A planarization process is then used to remove excess oxide. The remaining silicon nitride is used as an etch stop. In a modern sub-micron process, chemical-mechanical polishing (CW) is used to planarize the features.
Referring to FIG. 1A of a prior art process, the features are shown after having undergone CMP. Device 100 is formed on a substrate 110. STI regions 150 are separated by the SiO.sub.2 /SiN stacks 140. The stack 140 consists of the thin oxide layer 120 and a nitride layer 130. Following the planarization, the nitride is stripped with a wet cleaning process. The areas of stripped nitride can be used to provide regions of active areas separated by STI. Next, post CMP cleaning processes and a "sacrificial oxidation" pre-clean process step followed by growth of about 200 .ANG. to 300 .ANG. sacrificial oxidation layer prepares the active areas of the MOS transistor structure for subsequent processing.
The preceding processes may form STI oxide recesses near the top comers of the trenches. This is a significant challenge to overcome. Referring to FIG. 1B, the oxide recesses 160 are shown. These recesses cause a V.sub.t roll-off in narrow transistors, also known as the wrap around effect, owing to the gate oxidation thinning in subsequent processing and the higher electric field around the sharp top comers of the trenches near the active area 120a. Consequently, the top comer oxide recess enhances the wrap around effect and degrades the transistor performance of a device built in the active area 120a.
Accordingly, there is a need for a process that minimines the likelihood of forming such recesses that tend to degrade transistor performance.